View 74F195A_309475.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
74F195A 4-bit parallel-access shift register
Product specification IC15 Data Handbook 1996 Mar 12
Philips Semiconductors
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
FEATURES
* Shift right and parallel load capability * J - K (D) inputs to first stage * Complement output from last stage * Asynchronous Master Reset * Diode inputs
DESCRIPTION
The 74F195A is a 4-Bit Parallel Access Shift Register and its functional characteristics are indicated in the Logic Diagram and Function Table. This device is useful in a variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The 74F195A operates in two primary modes: shift right (Q0Q1) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is High, and is shifted one bit in the direction Q0Q1Q2Q3 following each Low-to-High clock transition. The J and K inputs provide the flexibility of the J-K type input for special applications, and by tying the two together the simple D-type input is made for general applications. The device appears as four common clocked D flip-flops when the PE input is Low. After the Low-to-High clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3 outputs. Shift left operation (Q3-Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input Low. All parallel and serial data transfers are synchronous, occurring after each Low-to-High clock transition. The 74F195A utilizes edge-triggering, therefore there is no restriction on the activity of the
J, K, Dn, and PE inputs for logic operation, other than the set-up and hold time requirements. A Low on the asynchronous Master Reset (MR) input sets all Q outputs Low, independent of any other input condition.
PIN CONFIGURATION
MR J K D0 D1 D2 D3 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q0 Q1 Q2 Q3 Q3 CP PE
SF00757
TYPE 74F195A
TYPICAL fMAX 180MHz
TYPICAL SUPPLY CURRENT (TOTAL) 40mA
ORDERING INFORMATION
DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F195AN N74F195AD PKG. DWG. # SOT 38-4 SOT 109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F195 D0-D3 D0 D3 Data inputs 74F195A 74F195 J, JK J-K J K or D type serial inputs 74F195A 74F195 CP Clock Pulse input (active rising edge) 74F195A 74F195 MR Q0-Q3, Q3 Master Reset input (active Low) 74F195A Data outputs 1.0/1.0 50/33 20A/0.6mA 1.0mA/20mA 1.0/1.0 2.0/0.066 20A/0.6mA 40A/40A 1.0/1.0 1.0/0.033 20A/0.6mA 20A/20A 1.0/1.0 1.0/0.033 20A/0.6mA 20A/20A 74F (U.L.) HIGH/LOW 1.0/0.033 LOAD VALUE HIGH/LOW 20A/20A
NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
1996 Mar 12
2
853-0024 16555
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
LOGIC SYMBOL
4 5 6 7
IEC/IEEE SYMBOL
SRG4 9 D0 D1 D2 D3 1 10 M1 R C2/1
9 2 10 3 1
PE J CP K MR Q0 Q1 Q2 Q3 Q3 11 2 3 4 5 6 7 1, 2J 1, 2K 1, 2D 1, 2D 14 13 12 11 15 14 13 12 15
VCC = Pin 16 GND = Pin 8
SF00758
SF00759
LOGIC DIAGRAM
CP PE 10 9
J
2
K
3 CP R S 15 Q Q Q0
MR D0
1 RD 4
D1
5 CP RD R S 14 Q Q1
D2
6 CP RD R S 13 Q Q2
D3
7 CP RD R S 12 Q Q 11 Q3 Q3
VCC = Pin 16 GND = Pin 8
SF00760
1996 Mar 12
3
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
FUNCTION TABLE
INPUTS MR L H H H H CP X PE X h h h h J X h l h l K X h l l h Dn X X X X X Q0 L H L q0 q0 Q1 L q0 q0 q0 q0 OUTPUTS OPERATING MODES Q2 L q1 q1 q1 q1 Q3 L q2 q2 q2 q2 Q3 H q2 q2 q2 q2 Reset (clear) Shift, set First stage Shift, reset First stage Shift, toggle First stage Shift, retain First stage
H = High voltage level h = High voltage level one setup time prior to Low-to-High clock transition L = Low voltage level l = Low voltage level one setup time prior to Low-to-High clock transition X = Don't care = Low-to-High clock transition dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to +VCC 40 0 to +70 -65 to +150 UNIT V V mA V mA C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 -18 -1 20 70 NOM 5.0 MAX 5.5 V V V mA mA mA C UNIT
1996 Mar 12
4
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER TEST CONDITIONSNO TAG MIN VO OH High level output voltage High-level VCC = MIN, VIL = MAX , VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX , VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX 74F195A 74F195A all others 74F195A -60 40 10%VCC 5%VCC 10%VCC 5%VCC 2.5 2.7 3.4 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -600 -150 58 V V A A mA mA mA TYP
NO TAG
UNIT MAX V V
VO OL VIK II IIH IIL IOS ICC
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3 Supply current (total)
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5V Tamb = +25C CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPHL tPLH Maximum clock frequency Propagation delay CP to Qn Propagation delay CP to Q3 Propagation delay MR to Qn Propagation delay MR to Q3 Load mode Shift mode Waveform NO TAG Waveform NO TAG Waveform NO TAG Waveform 2 Waveform 2 165 180 3.0 2.5 2.0 2.0 2.0 2.5 TYP 180 190 5.0 4.0 5.5 4.0 4.0 4.5 9.5 7.0 9.5 6.5 7.0 8.0 MAX VCC = +5V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN 150 170 2.5 2.0 2.5 2.0 2.0 2.0 10.0 7.5 9.5 7.0 7.0 10.0 MHz ns ns ns ns MAX UNIT
1996 Mar 12
5
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5V Tamb = +25C CL = 50pF, RL = 500 MIN tS(H) tS(L) th(H) th(L) tS(H) tS(L) th(H) th(L) tW(H) tW(L) tREC Setup time, High or Low J, K and Dn to CP Hold time, High or Low J, K and Dn to CP Setup time, High or Low PE to CP Hold time, High or Low PE to CP CP Pulse width High MR Pulse width Low Recovery time MR to CP Waveform 3 Waveform 3 Waveform 4 Waveform 4 Waveform NO TAG Waveform 2 Waveform 2 2.5 2.5 0.0 1.0 2.0 2.5 0.0 0.0 4.5 4.5 2.5 TYP MAX VCC = +5V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN 2.5 2.5 0.0 1.0 2.0 2.5 0.0 0.0 4.5 4.5 3.0 MAX ns ns ns ns ns ns ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fmax MR CP VM tw(H) tPHL Q3 tPLH Qn VM VM tPLH VM tPHL tPHL VM Qn tPLH VM CP VM VM tw(L) trec VM VM VM
SF00761
Q3
VM
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
SF00762
Waveform 3. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time
J, K, Dn SERIAL-SHIFT RIGHT VM ts(H) VM th(H) VM ts(L) VM th(L) PE VM ts(H) CP VM VM CP VM VM VM th VM ts(L) VM th PARALLEL LOAD
SF00763
Waveform 2.
Data Setup and Hold Times
Qn
RESPONSE
Qn=Qn-1
Qn=Dn
SF00764
Waveform 4.
Setup and Hold Times, Parallel Enable to Clock
1996 Mar 12
6
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
1996 Mar 12
7
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1996 Mar 12
8
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
NOTES
1996 Mar 12
9
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05096
Philips Semiconductors
yyyy mmm dd 10

▲Up To Search▲

Price & Availability of 74F195A

	To Download 74F195A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .